Creation of a PRBS is usually explained and implemented as applying a polynomial to a binary sequence; it can be illustrated by applying a number of XOR (exclusive OR) operations to a binary shift register.
FIG. 1 shows a simple model for PRBS generation illustrating a shift register 10 comprising one XOR unit 12 which performs a logical operation of exclusive OR with the 11th and 9th positions of the register to introduce the result in the 0-th position of the register. The output of the register issues a PRBS bit sequence.
The process of forming the bit sequence can be described by the following polynomial having two terms (i.e., w=2, not including the “1”):P=1+X9+X11According to the above polynomial, each position ai in the PRBS bit sequence can be formed as follows, using (w−1) XOR operations:ai=ai-9⊕ai-11Using indexes nj of complexity of a polynomial:ai=ai-n0⊕ai-n1where n0=9, n1=11,we may write down the process of forming a PRBS based on any given polynomial:
                                                                        p                =                                  1                  +                                                            ∑                                              0                        ≤                        j                        <                        w                                                              ⁢                                                                                  ⁢                                          x                                              n                        j                                                                                                        ;                                                                                          a                i                            =                                                ∑                                      0                    ≤                    j                    <                    w                                    ⊕                                ⁢                                                                  ⁢                                  a                                      i                    -                                          n                      j                                                                                                                              (        1        )            
As it has been accepted by now, the greater the “w” parameter, the wider the bus (i.e., the greater the number of the “S” parameter), the more complex the PRBS generation process will be from the point of time and memory consumption.
The above statement could be explained by the fact that, for forming any next binary position of the PRBS sequence, some particular previous binary positions of the PRBS sequence should be used. Based on the conventional model of the PRBS generation, one cannot calculate a following position of the PRBS sequence before the required previous positions of the sequence become known. However, the previous positions are also to be calculated based on some pre-previous positions of the PRBS stream. Consequently, if all S positions of a rather long pattern of PRBS sequence is to be created during one and the same generator's clock, this clock would most probably include a considerable number of iterative calculations (and a chain of XORs in the implementation) which means that a high speed clock is hardly achievable for wide buses.
In case the PRBS sequence be wholly stored in the memory, so that patterns of the sequence be issued just by reading them from the memory one after another, the memory would be excessively large since the periodicity of a complex PRBS pattern is quite great and is equal to 2K−1, where K=nw-1.
U.S. Pat. No. 5,034,906 describes a system for synchronizing a pseudorandom binary sequence signal with a time-delayed version of the same signal without the use of delay lines or programmable counters. This is accomplished by the use of two Pseudorandom Binary Sequence [PRBS] generators for producing the same PRBS signal. Each PRBS generator incorporates as a constituent component a serial shift register with M stages with the outputs of multiple stages fed back through can exclusive-OR to provide an input to the register, thereby to produce a clocked repetitive series of said sequence signal as inputs to each register. The states of shift register are numbered n such that (n−1) clock cycles elapse before the next start state. A start detect circuit is responsive to the start state of the pseudorandom binary sequence signal of the first generator for generating a synchronizing signal at that instant to force the second PRBS generator to be at a state in the binary sequence representing a delayed point in the sequence.
The solution of U.S. Pat. No. 5,034,906 is focussed on synchronizing the sequence. It should be mentioned, however, that the principle of a serial shift register does not allow obtaining a high speed wide bus PRBS generator.